1. Field of the Invention
The present invention generally relates to the forming in integrated form of bipolar transistors. More specifically, the present invention relates to the forming of the extrinsic base of such a transistor.
2. Description of the Related Art
FIGS. 1A to 1D illustrate, in partial simplified cross-section views, different steps of a known method for manufacturing an integrated circuit bipolar transistor.
As illustrated in FIG. 1A, a silicon oxide layer 3, a heavily-doped P-type polysilicon layer 5, and a silicon nitride layer 7 are formed on a lightly-doped N-type single-crystal silicon substrate 1.
Then, as illustrated in FIG. 1B, a window 9 is opened in nitride and polysilicon layers 7 and 5 to expose oxide layer 3. A silicon nitride spacer 11 is formed on the vertical wall of window 9.
At the next steps illustrated in FIG. 1C, oxide layer 3 is opened from the bottom of window 9 to expose substrate 1. Layer 3 is etched so that the formed recess extends from window 9 to under layer 5. A selective epitaxial growth of a heavily-doped P-type semiconductor material 13, silicon or silicon germanium, is then performed. The growth of material 13 is performed selectively on the exposed silicon portions. A central single-crystal silicon region 131 is thus formed on the upper surface of substrate 1 and a lateral polycrystalline region 132 is formed under polysilicon layer 5.
As illustrated in FIG. 1D, the method carries on with the forming of an L-shaped spacer 15 on the wall and the bottom of window 9. A heavily-doped N-type silicon layer 19 is deposited to fill window 9. Silicon layer 19 and nitride layer 7 are etched to only be left in place close to window 9. Polysilicon layer 5 is thus exposed.
The method carries on with steps not shown, especially of silicidation of silicon surfaces 5 and 19 and of forming of metallizations solid with these surfaces.
A bipolar transistor having substrate 1 as its collector, region 13 as its base, and layer 19 as its emitter has thus been formed.
A disadvantage of such a method lies in the epitaxial growth of base 13 described in relation with FIG. 1C. Indeed, region 13 comprises regions 131 and 132 of distinct crystal lattices. Polycrystalline region 132 adversely affects the nominal electric performances desired for the final transistor. Its effect is all the stronger as base region 13 is thin and as the base-emitter junction is small.
Further, the conditions of the selective growth of base 13 are relatively disadvantageous. Indeed, these conditions depend on the nature of the planar upper surface, that is, of layer 7. In the presence of silicon nitride, the selectivity of the silicon-germanium epitaxial growth requires a high-temperature epitaxy in the presence of chlorine.
Further, to optimize the electric performances of the resulting transistor, it has been shown that is was desirable for region 13 to comprise a P-type doped layer intended to form the base of the transistor encapsulated in a silicon-germanium portion (SiGe) comprising substitutional-site carbon inclusions (C). To be in substitutional site and obtain a single-crystal SiGeC lattice, the carbon must be incorporated upon epitaxy at a sufficiently low temperature. However, it has already been noted that, to be selective in the presence of nitride, the epitaxy must be performed at high temperature, on the order of 700° C. The presence of nitride layer 7 thus limits the amount of carbon that can be incorporated.